High speed test pattern transfer apparatus for semiconductor test system

ABSTRACT

A test pattern transfer apparatus is to improve overall throughput of a semiconductor test system which has an engineering work station for functioning as a host computer, a test controller for controlling an operation of the semiconductor test system and a pattern memory for generating test patterns transferred from a hard disk of the engineering work station. The test pattern transfer apparatus simplifies the pathways for transferring the test patterns so as to reduce the time required for the pattern transfer by directly transferring the test pattern from the work station to the pattern memory without passing through the test controller. The test pattern transfer apparatus includes an interface controller whereby the test pattern from the engineering work station is either directly transferred to the pattern memory or indirectly transferred to the pattern memory through the test controller.

FIELD OF THE INVENTION

This invention relates to a high speed transfer apparatus fortransferring test patterns from a host computer to a pattern memory in asemiconductor test system.

BACKGROUND OF THE INVENTION

In a semiconductor test system, a large amount of test patterns to beused for semiconductor testing are read out from a disk drive of a workstation and transferred to a pattern memory every time when the testitems for an LSI are changed.

A conventional method, used in such a semiconductor test system, fortransferring the test patterns from the disk drive of the work stationto the pattern memory in a buffer memory will be described in thefollowing with reference to FIGS. 3-5.

As shown in FIG. 3, the conventional semiconductor test system iscomprised of an EWS (Engineering Work Station) 12, a tester controller13 and a buffer memory 14. These three components are situated apartwith certain distances from each other and connected by bus cables whichinterfere therebetween.

The EWS 12 is mainly utilized as a host computer for producing testpatterns and performing debugging. The EWS 12 includes a disk drive 11which is a large capacity storage medium to store the test patternsgenerated by the EWS 12.

The tester controller 13 is a control processor which manages thesemiconductor test system itself.

A pattern memory 14b is a high speed memory which stores a test pattern100 for testing an LSI which is transferred from the EWS 12. The patternmemory 14b applies the test pattern 100 to a device under test.

Reference numerals 12c, 13c, 13d and 14a are interface circuits whichdeal with differences in the format or speed of data between the buscables in which data is transferred. The EWS 12 includes a temporarybuffer memory 12b. The tester controller 13 includes a temporary buffermemory 13b.

The test pattern 100 is transferred from the disk drive 11 in the EWS 12to a pattern memory 14b of the buffer memory 14 through pathwaysdescribed in the following.

Namely, the test pattern 100 stored in the disk drive 11 is transferredto the memory 12b in the EWS 12 via a pathway 15 through the interface12a.

Then, via a pathway 42, the test pattern 100 is transferred from thememory 12b to the memory 13b in the tester controller 13 through theinterfaces 12c and 13c.

Next, via a pathway 43, the test pattern 100 is transferred from thememory 13b to the memory 14b in the buffer memory 14 through theinterfaces 13d and 14a.

The data transfer by means of the pathway 15 includes the memoryread-out from the disk drive 11 to the memory 12b through the interface12a.

There are two ways to transfer the data by reading and writing in thememory 12b of the EWS 12 to the memory 13b of the tester controller 13through the pathway 42 as follows:

(i) Data transfer by means of a program I/O in the EWS 12.

(ii) Data transfer from the EWS 12 to the test controller 13 by means ofa DMA (Direct Memory Access) hardware.

FIG. 4 explains the hardware structure with respect to the above datatransfer (i) and (ii).

In the case of (i), a map register 13f is utilized for the data transferwhich is performed by the program I/O. The map register 13f holds anoffset value relative to the memory 13b of the test controller 13viewing from a CPU 12d of the EWS 12. When accessing the memory 13b ofthe test controller 13 by the CPU 12d of the EWS 12, this offset valueis added to an address coming from the EWS 12 side and transmitted tothe address bus B; then, data of the memory 12b is transferred to thememory 13b.

In the case of (ii) for the direct memory access, a DMA address counter12e and a DMA address counter 13e are utilized for the data transfer.

The DMA address counter 12e is used for the read-out and write-in accessof the memory 12b. Before the direct memory access is taken place, theCPU 12d stores a start address of the memory 12b in the DMA addresscounter 12e through the data bus A and determines a number of words tobe transferred. When the CPU 12d initiates the direct memory access, theDMA address counter 12e increments an address value which corresponds tothe number of words per one time for the address bus A every time whenone cycle of the DMA transfer is completed. This incrementing process iscontinued until the transfer for all of the predetermined number ofwords is completed. After the transfer of the predetermined number ofwords is performed, the data transfer by means of the DMA transfer iscompleted by interrupting the CPU 12d and notifying the completion ofthe process.

The DMA address counter 13e is used in the read-out and write-in accessof the memory 13b of the tester controller 13. The CPU 12d of the EWS 12stores a start address of the memory 13b in the DMA address counter 13ethrough the data bus A before the direct memory access is started. Whenthe CPU 12d of the EWS 12 initiates the direct memory access, the DMAaddress counter 12e increments an address value for the address bus Aevery time when one cycle of the DMA transfer is completed, insynchronism with the DMA address counter 12e, wherein the address valuecorresponds to the number of words per each time. The difference fromthe DMA address counter 12e is that there is no prearrangement of thedata size. Thus the data transfer by means of the DMA transfer iscompleted by a control signal transmitted from the DMA address counter12e.

In FIG. 3, there are two ways of the reading and writing access for thememory 14b of the buffer memory 14 by the memory 13b of the testercontroller 13 through the pathway 43 as follows:

(iii) Data transfer by means of a program I/O in the test controller 13.

(iv) Data transfer between the test controller 13 and buffer memory 14by means of DMA (Direct Memory Access) hardware.

FIG. 5 explains the hardware structure with respect to the above (iii)and (iv) situations.

In the case of (iii), a map register 13j operates in a similar manner asthe map register 13f in FIG. 4 whereby the data transfer is taken placeby means of the program I/O.

In the case of (iv), a DMA address counter 13g and a DMA address counter13h operate in a similar manner as the DMA address counter 12e and theDMA address counter 13e in FIG. 4 whereby the data transfer is takenplace by means of the DMA.

As in the foregoing, the test pattern 100 of the disk drive 11 is readout by the memory 12b of the EWS 12 and transferred to the memory 13b ofthe tester controller 13; then the test pattern is transferred to thepattern memory 14b of the buffer memory 14. If the volume of the testerpattern is small, the data transfer time is short in comparison with thetesting time of the LSI. Thus, the access time for the reading andwriting process is will not be affected by the data transfer. However,the volume of the test pattern has been largely increased with therecent increase of the density in the LSI. Accordingly, the reading andwriting access time in the transfer time relative to the LSI testingtime has been greatly increased, resulting the lowered throughput.

SUMMARY OF THE INVENTION

Therefore, it is an object of the present invention to shorten the datatransfer time by minimizing the transfer route for the test patterns soas to improve the throughput of the semiconductor test system.

In the present invention, the test pattern 100 from the engineering workstation EWS 12 is either directly transferred to the buffer memory 14through an interface 13a or indirectly transferred to the buffer memory14 through the interface 13a and the test controller 13.

The present invention realizes a high speed test pattern transferapparatus to be used in the semiconductor test system. The test patterntransfer apparatus comprising: the engineering work station EWS 12; thetester controller 13; the buffer memory 14; the interface 12c providedin the EWS 12 for interfacing with the tester controller 13; theinterface 14a provided in the buffer memory 14 for interfacing with thetester controller 13, wherein, data in the memory 12b can be directlytransferred to the pattern memory 14b, between the tester pattern 100stored in the disk drive 11 in the EWS 12 and buffer memory 14, withouttemporarily transferring the data to the memory 13b.

The interface 13a consists of: an arbiter 13k that controls thesimultaneous access and data flows; multiplexers MUXA 13n and MUXB 13p;DMA address counters 13e, 13g and 13h and map registers 13f and 13j thattransfer data stored in the memory 12b of the EWS 12 to the memory 13bof the tester controller 13, and, further transfer the data in thememory 13b to the pattern memory 14b of the buffer memory 14; a DMAaddress counter 13r and map register 13m for directly transferring thedata in the memory 12b to the pattern memory 14b.

In the high speed transfer system of the present invention, the testpattern 100 stored in the memory 12b of the EWS 12 is transferredthrough a pathway 16 as follows: when the data is transferred by theprogram I/O, an address of the map register 13m is arranged to be offsetrelative to the address bus C, viewing from the program I/O of the EWS12.

With respect to the DMA transfer operation through the pathway 16, theDMA address counter 13r is utilized for an access of the pattern memory14b of the buffer memory. Then, an input (a) is selected in themultiplexer MUXA 13n. Similarly, an input (a) is selected in themultiplexer MUXB 13p. Since the tester pattern data is directlytransferred to the pattern memory 14b of the buffer memory 14 withoutbeing transferred to the memory 13b of the tester controller 13, thehigh speed data transfer is thereby achieved.

Since the arbiter 13k, multiplexers MUXA 13n and MUXB 13p function tocontrol the simultaneous access operations and data flows of the datatransfer pathways 16, 42 and 43, the data transfer is smoothly performedwithout causing the EWS 12, tester controller 13 and buffer memory 14 tobe affected each other.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the data transfer pathways of thepresent invention.

FIG. 2 is a detailed block diagram showing an example of the interfacefor the data transfer in the present invention.

FIG. 3 is a block diagram showing the data transfer pathways of theprior art.

FIG. 4 is a detailed block diagram showing an example of the interfacein the data transfer of the prior art.

FIG. 5 is a detailed block diagram showing another example of theinterface in the data transfer of the prior art.

PREFERRED EMBODIMENT OF THE PRESENT INVENTION

The present invention will be discussed with reference to FIG. 1 and 2in the following.

FIG. 1 shows the relationship between the data transfer pathways 16, 42and 43 according to the present invention.

The only difference from the prior art resides in the interface 13awhich performs the functions of the interfaces 13c and 13d in the priorart of FIGS. 3-5.

In the present invention, the following data transfer operations asstated in (1)-(6) can be achieved by means of the interface 13a. In thiscase, the operations (1)-(4) are the same operations which are conductedby the pathways 42 and 43 in the prior art. The operations (5) and (6)are the high speed data transfer by means of the pathway 16, which arenewly added to the present invention.

(1) Data transfer by the program I/O in the EWS 12.

(2) Data transfer between the EWS 12 and tester controller 13 by meansof the DMA (Direct Memory Access) hardware.

(3) Data transfer by the program I/O in the tester controller 13.

(4) Data transfer between the tester controller 13 and buffer memory 14by means of the DMA hardware.

(5) Data transfer between the EWS 12 and the buffer memory 14 by meansof the program I/O.

(6) Data transfer between the EWS 12 and the buffer memory 14 by meansof the DMA hardware.

The structure of the interface 13a of the present invention is discussedin detail in FIG. 2.

The interface 13a consists of the DMA address counters 13e, 13g, and 13hand map registers 13f and 13j all of which are conventionally known, andnewly added components of an arbiter 13k, a DMA address counter 13r, amap register 13m and multiplexers MUXA 13n and MUXB 13p.

The arbiter 13k and multiplexers 13n and 13p control the simultaneousaccess and address and data flows according to the priority of the datatransfer as described in the above data transfer (1)-(6).

The DMA address counter 13r is utilized for the DMA transfer between thememory 12b of the EWS 12 and buffer 14. The DMA address counter 13r hasan identical function to the DMA address counter 13e.

An address offset with respect to the program I/O of the EWS 12 isprovided for the map register 13m relative to the address bus C therebythe map register 13m is used for the data transfer by means of theprogram I/O in the data transfer (5).

The MUXA 13n multiplexes the address data. An input (a) of the MUXA 13nis selected when the data transfer operations as noted in (5) and (6)are taken place. And an input (b) of the MUXA 13n is selected when thedata transfer operations of (1)-(4) are taken place.

Conversely, the MUXB 13p multiplexes the data. An input (a) of the MUXB13p is selected when the data transfer operations noted in (5) and (6)are taken place. An input (b) is selected when the data transferoperations of (1)-(4) are taken place.

When the data transfer operations of (1)-(4) are taken place, the input(b) is selected in each of the MUXA 13n and MUXB 13p. The data transferoperations of (1)-(4) use the conventional DMA address counters 13e, 13gand 13h and the map registers 13f and 13j, wherein these elementsoperate as described in the conventional invention.

The data transfer operations of the present invention in (5)-(6) aredescribed in the following.

As in FIG. 1, the test pattern 100 which is read out in the memory 12bof the EWS 12 is transferred to the pattern memory 14b of the buffermemory 14 through the pathway 16 by means of the above data transferoperations (5)-(6). Namely, in case of the program I/O in the operation(5), the offset stored in the map register 13m is added to the addressof the memory 12b of the EWS 12. Then, the input (a) is selected in theMUXA 13n and MUXB 13p, and the test pattern 100 is transferred inhigh-speed to the pattern memory 14b of the buffer memory 14. In case ofthe DMA transfer in the operation (6), the DMA address counter 12e isused to access the memory 12b of the EWS 12. The DMA address counter 13ris used to access the pattern memory 14b of the buffer memory 14. Then,the input (a) is selected in the MUXA 13n and MUXB 13p and the testpattern 100 is transferred in high-speed.

In the foregoing, although the test pattern 100 is used as data to betransferred, it is possible to adopt other data. Moreover, although thedata is transferred to the pattern memory 14b of the buffer memory 14,it is apparent that other storage medium can equally be used for thedata transfer of the present invention.

Since the present invention is structured as has been described in theforegoing, it has the following effects.

Namely, in the conventional invention, the tester pattern stored in thememory of the EWS of the host computer is first transferred to thememory of the test processor and then transferred to the pattern memoryof the buffer memory. If the volume of the test patterns of the LSI islarge, the conventional process is disadvantageous because it takes toolong a time to transfer the test patterns relative to the overalltesting time. Thus, the present invention provides the pathway that candirectly transfer the test pattern from the memory of EWS in the hostcomputer to the pattern memory in the buffer memory without making anaccess to the memory of the test processor, in addition to theconventional pathways. Furthermore, the address counter and the mapregister are added thereto in order to transfer the test pattern datadirectly to the buffer memory. Moreover, the arbiter and multiplexersare provided in order to control the simultaneous access according tothe priority of the added transfer pathway and the address and dataflows. Therefore, the present invention is able to achieve thehigh-speed transfer of the pattern data.

Thus, the present invention has an advantage that the transfer pathwaysfor the test pattern in the semiconductor test system are moresimplified than the conventional invention so as to improve thethroughput of the semiconductor testing by shortening the data transfertime.

What is claimed is:
 1. A high speed test pattern transfer apparatus fora semiconductor test system, comprising:an engineering work station EWS(12) which functions as a host computer of said semiconductor testsystem; a tester controller (13) which receives data from said EWS (12)and controls a test operation of said semiconductor test system; abuffer memory (14) provided in said semiconductor test system forstoring test patterns (100) produced by said EWS (12) and generatingsaid test patterns to apply said test patterns (100) to a semiconductordevice under test; a first interface (12c) provided in said EWS (12) forinterfacing between said EWS (12) and said tester controller (13); asecond interface (14a) provided in said buffer memory (14) forinterfacing between said tester controller (13) and said buffer memory(14); and a third interface (13a) provided in said tester controller(13) and arranged such that; said test patterns (100) in said EWS (12)are either directly transferred to the buffer memory (14) through saidthird interface (13a) or indirectly transferred to said buffer memory(14) through said third interface (13a) and said tester controller (13).2. A high speed test pattern transfer apparatus of claim 1, wherein saidthird interface (13a) comprising:an arbiter (13k) for monitoring dataflow in said third interface (13a) and controlling simultaneous accessand data flow between said EWS (12) , said tester controller (13) andsaid buffer memory (14); multiplexer means (13n, 13p) for switchingbetween said test patterns transmitted directly from said EWS (12) andindirectly from said tester controller (13) to be supplied to saidbuffer memory (14); DMA address counters (13e, 13g and 13h), and mapregisters (13f, 13j), for transferring data stored in a memory (12b) ofsaid EWS (12) to a memory (13b) of said tester controller (13), and,further, transferring the data in said memory (13b) to a pattern memory(14b) of said buffer memory (14); and a DMA address counter (13r) and amap register (13m) for directly transferring the data in said memory(12b) to said pattern memory (14b).
 3. A high speed test patterntransfer apparatus of claim 1, wherein said test patterns (100) aretransferred from said EWS (12) to said tester controller (13) and fromsaid tester controller (13) to said buffer memory (14) either by aprogram transfer process or a direct memory access (DMA) process.
 4. Ahigh speed test pattern transfer apparatus of claim 1, wherein said testpatterns (100) are transferred from said EWS (12) to said buffer memory(14) either by a program transfer process or a direct memory access(DMA) process.
 5. A high speed test pattern transfer apparatus of claim1, wherein said third interface (13a) comprising:multiplexer means (13n,13p) for switching between said test patterns transmitted directly fromsaid EWS (12) and indirectly from said tester controller (13) to besupplied to said buffer memory (14); an address counter (13r) fordirectly transferring said test patterns from said EWS (12) to saidbuffer memory (14) through a first state of said multiplexer means by adirect memory access (DMA) process; and a map register (13m) fordirectly transferring said test patterns from said EWS (12) to saidbuffer memory (14) through said first state of said multiplexer means bya program transfer process.
 6. A high speed test pattern transferapparatus of claim 5, wherein said third interface (13a) furthercomprising:address counters (13e, 13g, 13h) for transferring said testpatterns from said EWS (12) to said tester controller (13) and from saidtester controller (13) to said buffer memory (14) through a second stateof said multiplexer means by said direct memory access (DMA) process;and map registers (13f, 13j) for transferring said test patterns fromsaid EWS (12) to said tester controller (13) and from said testercontroller (13) to said buffer memory (14) through said second state ofsaid multiplexer means by said program transfer process.